3DCT-20: Seventh IEEE International Workshop on Testing Three-Dimensional, Chiplet-Based, and Stacked ICs Virtual San Jose, CA, United States, November 6, 2020 |
Conference website | http://3dctest.tttc-events.org/ |
Submission link | https://easychair.org/conferences/?conf=3dct7 |
Abstract registration deadline | September 28, 2020 |
Submission deadline | October 16, 2020 |
The 3DC-TEST Workshop focuses on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While this approach offer the advantages of heterogeneous integration, small form-factor, high bandwidth/performance, and low power dissipation, there are many open issues with respect to testing such products. The 3DC-TEST Workshop is a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners.
3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC).
Submission Instructions – Prospective authors are invited to submit as PDF files: (a) a one paragraph intent to submit by Sep 28; (b) an extended abstract of at least two pages by Oct. 16. Detailed submission instructions can be found at http://3dtest.tttc-events.org. Submissions will be evaluated on originality, technical soundness, and presented results.
Publications – The workshop will make available to all its registered participants an electronic workshop digest (EWD), which includes all material that authors/presenters are willing to contribute: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal journal, leveraging the audience feedback and discussions on the paper presentation at the 3DC-TEST Workshop.
Areas of Interest:
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General Co-Chairs:Erik Jan Marinissen – imec (BE), Yervant Zorian – Synopsys (US)
Program Chair:Bapi Vinnakota – Broadcom (US)
Finance Chair:Chen-Huan Chiang – Intel (US)
Industrial Chair:Marc Hutner – Teradyne (CAN)
Panel Chair: E. Jan Vardaman – TechSearch (US)
Virtualization Chair: Stefano di Carlo – Polit. Torino (IT)
Publicity Chair: Françoise von Trapp–3DInCites (US)
Web Chair: Hardi Selg – TU Tallinn (EE)
Program Committee Members:
- Saman Adham – TSMC (CAN)
- Dave Armstrong – Advantest (US)
- Sandeep Bhatia – Google (US)
- Krish Chakrabarty – Duke Univ. (US)
- Sreejit Chakravarty – Intel (US)
- Kun Young Chung – Qualcomm (US)
- Jon Colburn – Nvidia (US)
- Eric Cormack – DfT Solutions (UK)
- Adam Cron – Synopsys (US)
- Alfred Crouch – Amida (US)
- Marie-Lise Flottes – LIRMM (FR)
- Ferenc Fodor – IMEC (BE)
- Paul Franzon – NC State Univ. (US)
- Phil Garrou – MCNC (US)
- Sandeep K. Goel – TSMC (US)
- Hailong Jiao – Peking University (CN)
- Hongshin Jun – Juniper Networks (US)
- Shuichi Kameyama – Ehime Univ. (JP)
- Chien-Mo Li – NTU (TW)
- Amit Majumdar – Xilinx (US)
- Teresa McLaurin – ARM (US)
- Benoit Nadeau-Dostie – Mentor (CAN)
- Brandon Noia – AMD (US)
- Christos Papameletis – Cadence (US)
- Mike Ricchetti – Synopsys (US)
- Saghir Shaikh – Broadcom (US)
- Raffaele Vallauri – Technoprobe (IT)
- Pascal Vivet – CEA-Leti (FR)
- Michael Wahl – Univ. of Siegen (DE)