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Author
:
K. Rajasekhar
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Implementation of 24 Bit Multiplier Using Parallel Multiplication with Sorting Based Binary Counters for VLSI Applications
Pinniboyina Anand Venkat Seshu Babu
and
K. Rajasekhar
EasyChair Preprint 8653
Keyphrases
24 bit multiplier
,
approximate 4:2 compressor
,
Binary counters
,
one-hot code
,
sorting network
.
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