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Determine the Interconnection of a Hardware Implementation for DSP Applications

EasyChair Preprint no. 2257, version 2

Versions: 12history
5 pagesDate: November 13, 2020


In VLSI design the hardware is implemented with some objective and constrain functions (as lower number of hardware used). When the system contains a lot of processing elements (PEs) and memory (registers), the cost of the interconnections becomes of great issue and must be minimized. Work in the field of determination of the interconnection for a hardware implementation is not very common. In high-level synthesis it is usually considered the time scheduling and processor assignment from a given DFG. However, the cost of interconnection is not widely discussed and is left to a VHDL system to determine it. In this paper, a technique for determining the interconnection in a hardware design is proposed. The objective function is the minimum number if hardware used and the constrain is minimum iteration period bound. This interconnection is shown to accomplish cost optimality in terms of minimizing the number of multiplexers used.

Keyphrases: Datapath, dfg, High-Level Synthesis, Multiplexers

BibTeX entry
BibTeX does not have the right entry for preprints. This is a hack for producing the correct reference:
  author = {Jehad Ahmad Ghanim and Ali Shatanawi},
  title = {Determine the Interconnection of a Hardware Implementation for DSP Applications},
  howpublished = {EasyChair Preprint no. 2257},

  year = {EasyChair, 2020}}
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