A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator

EasyChair Preprint 788

Abstract

This demonstration presents on-chip integrated digital low-dropout (DLDO) regulator based countermeasures for encryption engines against side channel analysis (SCA) attacks. DLDOs, a critical power management block, are increasingly integrated with modern SoC systems for ultra fine-grained power management and point of load regulation. This demonstration for the first time leverages DLDOs along with some circuit techniques to enhance SCA resistance of advanced encryption standard (AES) engines and presents experimental results and analysis. Our poster will show the motivation behind the proposed work, overall architecture and details about measurement setup, analysis techniques and side channel attack results with CPA/CEMA for two hardware implementations of AES algorithm - parallel AES (P-AES) and serial AES (S-AES).

Keyphrases: Advanced Encryption Standard, Electromagnetic, Security, Side Channel Analysis Attacks, experimental demonstration, leakage, power

@booklet{EasyChair:788,
  author    = {Arvind Singh and Monodeep Kar and Sanu Mathew and Anand Rajan and Vivek De and Saibal Mukhopadhyay},
  title     = {A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator},
  howpublished = {EasyChair Preprint 788},
  year      = {EasyChair, 2019}}